1. Field of the Invention
The present invention relates to an imaging apparatus.
2. Description of Related Art
A so-called column analog-to-digital converter (ADC) type solid-state imaging apparatus in which an AD conversion function is embedded in a column unit provided to correspond to each column of a pixel array disposed in a matrix in an imaging unit has been proposed. As AD conversion schemes, (1) a sequential comparison AD conversion scheme, (2) a single-slope AD conversion scheme, (3) a cyclic AD conversion scheme, (4) a ΔΣ AD conversion scheme, and the like have been proposed.
In the single-slope AD conversion scheme, AD conversion is performed as follows (for example, see Japanese Unexamined Patent Application, First Publication No. 2005-303648). An analog pixel signal read in a row unit from each pixel of the imaging unit via a vertical signal line is compared to a reference signal having a ramp-shaped waveform, so that a pulse signal having a magnitude (pulse width) in a time-axis direction corresponding to a magnitude of the pixel signal is generated. In the period of the pulse width of the pulse signal, a clock of a predetermined frequency is counted. A count value generated in the count operation becomes digital data corresponding to a magnitude of the pixel signal.
Recently, as means for speed-up of the single-slope AD conversion scheme, an column ADC type solid-state imaging apparatus using a time-to-digital converter (TDC) type AD conversion scheme has been proposed. As an example of a solid-state imaging apparatus using a TDC type AD conversion circuit, a configuration described in Japanese Unexamined Patent Application, First Publication No. 2008-92091 is known. FIG. 12 illustrates a part of a configuration of the TDC type AD conversion circuit when an oscillation circuit as a so-called “asymmetric oscillation circuit” is used as a voltage controlled oscillator (VCO) of an AD conversion circuit. First, the configuration and operation of the circuit of FIG. 12 will be described.
The circuit illustrated in FIG. 12 includes a VCO 1100, a latch unit 1108, a count unit 1105, a detection circuit 1107, and an encoding circuit 1106. The VCO 1100 includes an oscillation circuit in which seventeen delay units (NAND circuits NAND[0] to NAND[16]) are connected in a ring shape. The latch unit 1108 latches lower phase signals output from the VCO 1100. The lower phase signals include a plurality of phase signals CK[0] to CK[15] having phases different from each other. The count unit 1105 has a counter circuit which counts a lower phase signal CK[15] from the NAND circuit NAND[15] output through the latch unit 1108 as a count clock. The detection circuit 1107 detects a predetermined logic state based on the lower phase signals CK[0] to CK[15] latched in the latch unit 1108. The encoding circuit 1106 encodes the logic state detected by the detection circuit 1107 into a binary number.
A start pulse StartP is input to one input terminal of the NAND circuit NAND[0] constituting the VCO 1100 and an output signal of the NAND circuit NAND[16] is input to the other input terminal thereof. A power supply voltage VDD is input to one input terminal of each of the NAND circuits NAND[1] to NAND[15] and an output signal of the NAND circuit of a previous stage is input to the other input terminal thereof. The power supply voltage VDD is set to a high level during an operation period of the AD conversion circuit. An output signal of the NAND circuit NAND[13] is input to one input terminal of the NAND circuit NAND[16] and an output signal of the NAND circuit NAND[15] of a previous stage is input to the other input terminal thereof. An output signal of the NAND circuit NAND[13] is input to the NAND circuit NAND[16] three stages later, in addition to the NAND circuit NAND[14] one stage later.
A signal based on the start pulse StartP input to the NAND circuit NAND[0] is transmitted through two types of paths and passes through the NAND circuits NAND[0] to NAND[16]. A first path is a path to which a signal is transmitted through a signal line which connects the other input terminal of each NAND circuit with an output terminal of the NAND circuit of the previous stage thereof. A second path is a path (a bypass path) to which a signal output from the NAND circuit NAND[13] is transmitted through a signal line which connects the output terminal of the NAND circuit NAND[13] with an input terminal of the NAND circuit NAND[16]. The signal transmitted through the second path reaches the NAND circuit NAND[16] by bypassing the NAND circuits NAND[14] and NAND[15] without passing through the NAND circuits NAND[14] and NAND[15] on the first path. By the above configuration, a feed forward loop is formed and thus the so-called “asymmetric oscillation circuit” is configured.
Next, an operation of the circuit illustrated in FIG. 12 will be described. FIG. 13 illustrates waveforms of the start pulse StartP and the lower phase signals (phase signals CK[0] to CK[16]) from the VCO 1100. The horizontal direction of FIG. 13 represents time and the vertical direction of FIG. 13 represents voltage. First, a logic state of the start pulse StartP is changed from an L (low) state to an H (high) state, such that the VCO 1100 starts a transition operation. In the transition operation, the logic states of the phase signals output from the NAND circuits constituting the VCO 1100 are changed in order. Simultaneously when the VCO 1100 starts the transition operation, the count unit 1105 starts a count and a reference signal generation unit (not illustrated) starts to generate a ramp wave (a reference signal). The ramp wave generated by the reference signal generation unit is a signal of which the level increases or decreases in one direction over time.
The analog signal and the ramp wave which are targets of the AD conversion are input to a comparison unit (not illustrated). In parallel with this, the phase signals CK[0] to CK[15] are input to the latch unit 1108 and the phase signal CK[15] is input to the count unit 1105 through the latch unit 1108. At the timing at which voltages of the analog signal and the ramp wave input to the comparison unit are substantially the same, a comparison output CO of the comparison unit is inverted. At this time, the latch unit 1108 latches the logic state corresponding to the lower phase signals CK[0] to CK[15] and the count unit 1105 latches a count value (an upper count value). The lower phase signals (phase signals CK[0] to CK[15]) latched by the latch unit 1108 are encoded (binarized) by the detection circuit 1107 and the encoding circuit 1106 and thus become lower data of digital data, and the upper count value latched by the count unit 1105 becomes upper data of the digital data. Thereby, digital data corresponding to the level of the analog signal is obtained.
For encoding the lower phase signals, for example, it is preferable to detect whether the logic states of two phase signals are predetermined states in time series while changing the phase signal of a comparison target (for example, see Japanese Unexamined Patent Application, First Publication No. 2012-191269). Specifically, a method of detecting that the logic states of the two lower phase signals output from the two NAND circuits are the predetermined logic states, for example, “01” (L state and H state), is performed in time series.